The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under generates numerous problems challenging the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric interlayer on a semiconductor substrate, typically doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric material, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed. Planarization, as by CMP, is then performed.
The drive to increased density and attendant shrinkage in feature size generates numerous problems. For example, as feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.50 microns and below, such as 0.375 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly with a dielectric material and obtain adequate step coverage.
Another problem generated by miniaturization relates to the RC time constant. Although semiconductor devices are being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, therefore, requires conductive lines having a high aspect ratio, i.e., conductor height to conductor width of greater than one, with reduced interwiring spacings. As a result, capacitive coupling between conductive lines becomes a primary limitation on circuit speed. If intrametal capacitance is high, the possibility for electrical inefficiencies and inaccuracies increase. It is recognized that a reduction in capacitance within multi-level metallization systems will reduce the RC time constant between the conductive lines.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect technology. HSQ is relatively carbon free, thereby rendering it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid poison via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C.; it does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. in intermetal applications. As deposited HSQ is considered a relatively low dielectric constant material with a dielectric constant of about 2.9-3.0, vis-a-vis silicon dioxide grown by a thermal oxidation or chemical vapor deposition which has a dielectric constant of about 3.9-4.2. The mentioned dielectric constants are based on a scale wherein 1.0 represents the dielectric constant of air.
It would be advantageous to employ HSQ as a dielectric interlayer, particularly in view of its low dielectric constant vis-a-vis conventional silicon oxide interlayers. However, in attempting to employ HSQ as a dielectric interlayer, it was found that cracking undesirably occurred, particularly in high stress areas, such as proximate leading and/or trailing conductive features of a dense array of conductive lines bordered by an open field.
For example, adverting to FIG. 1, a conductive pattern, such as a patterned metal layer comprising metal features with gaps therebetween, is formed on dielectric layer 10. The depicted patterned metal layer generally comprises a dense array of metal features including leading metal feature 11A and trailing metal feature 11B, wherein the metal features are separated by gaps 12, typically less than about 1 micron. A patterned metal layer having a feature size of about 0.50 microns typically contains gaps 12 extending about 0.375 microns. Leading metal feature 11A and trailing metal feature 11B border an open field, which generally extends greater than about 1 micron, such as greater than about 1.5 microns, e.g., greater than about 2 microns.
During experimentation conducted, a layer of HSQ was deposited on the patterned metal layer at a thickness sufficient to fill gaps 12 and serve as a dielectric interlayer, e.g., greater than about 8,000-10,000 .ANG.. It was found, however, that cracking occurred, particularly in high stress areas wherein a stepped portion was formed, as proximate leading metal feature 11A and trailing metal feature 11B bordering an open field, indicated by arrows 14 and 15, respectively.
Cracking in dielectric interlayers creates serious problems which negatively impact production throughput and device reliability. For example, cracks serve as trapping centers for contaminant particles and cause delamination.
Accordingly, there exists a need for semiconductor technology enabling the use of HSQ as a dielectric interlayer. There also exists a need for semiconductor technology enabling the use of HSQ as a dielectric interlayer in highly integrated semiconductor devices having design features of about 0.25 microns and under.